TeraRecon develops advanced processor to handle CT overload

December 20, 2000

By Greg FreiherrIn March 2001, TeraRecon plans to release the XT 2.0 processor, which is designed specifically to handle multislice CT data. This processor promises to help relieve the data overload that could occur with the coming release of eight- and

By Greg Freiherr

In March 2001, TeraRecon plans to release the XT 2.0 processor, which is designed specifically to handle multislice CT data. This processor promises to help relieve the data overload that could occur with the coming release of eight- and 16-slice CT scanners.

Early adopters of quad-slice scanners are already struggling to keep up, relying on multiplanar reformatting and thick slices to work through the data. The next generation of scanners could swamp them. Three-dimensional reconstructions and computer-aided detection tools may help, but only if the computing power is there to handle the data. TeraRecon hopes to provide the answer.

The programmable XT 2.0 will operate at 125 MHz, feature two gigabytes per second of memory bandwidth, and have a floating point rather than depending on integers, as current processors do.

"It is a very fast back projection accelerator," said Sjef Ten Den, an engineer at Netherlands-based Arcobel Graphics, which is collaborating with TeraRecon to develop advanced processing technology. "The whole architecture is tuned to work on images in 2-D and 3-D."

The XT 2.0 will be only the first in a series of processors that TeraRecon intends to launch. The plan is to improve the computing power of each new processor to keep pace with new CT scanner releases.

Company strategists view the personal computer as an ally in their battle to supply advanced computing capabilities. The XT 2.0 and its successors are designed to work with the PC motherboard, selectively computing bits of information as they arrive, then pushing reconstructed slices into the memory of the PC for later postprocessing. Data are processed a split second after being captured by the detector, appearing on a display screen slice by slice as the patient moves through the gantry.

"Progress is being driven by the Intels of this world and we are going to hitch (a ride) on their carriages," said Horst Bruning, Ph.D., vice president of engineering at TeraRecon.

The computing engine developed by TeraRecon and Arcobel Graphics has already proven itself as part of a quad-slice scanner. The processor produces images from all four detector arrays on the fly, reconstructing individual slices in about 100 msec.

"Our processor can do very fast Fourier transform, fast interpolation, and fast back projection," Bruning said.

He refused to name the manufacturer of the CT device in which these capabilities were demonstrated. TeraRecon is known to have worked with Hitachi in the past. Bruning would not confirm whether this company is the developer of the quad-slice scanner, noting only that the scanner was built by a Japanese company.

Regardless, no single manufacturer need be the sole beneficiary of R&D by TeraRecon and Arcobel. The two companies hope to sell processors to as many equipment manufacturers as possible, and CT represents only one opportunity. Cardiovascular MRI will require volumetric reconstructions of the beating heart and blood flow. Rotational angiography will have similar requirements.

Bruning is most excited, however, about diagnostic ultrasound, despite the cost margins in ultrasound scanners; the price of the finished product is only about a third the price of an MRI or CT machine.

"(Cost) is tight in ultrasound, but ultrasound has been doing the job with ASICs (application specific integrated circuits), and if these ASICs can be replaced by a very fast signal processor, there might be a price advantage, because you can very quickly adapt (the system to run) new algorithms," Bruning said, noting that ASICs are not as flexible as programmable processors.

Ultrasound is appealing because the number of scanners that might be sold is much higher than for CT or MRI. TeraRecon must sell a lot of its processors in order to amortize its R&D investment. Development on the processor built into the Japanese CT, for example, began in 1990. Its development, and that of its successors, is labor intensive.

"It takes a lot of highly paid engineers to do this," Bruning said. "A processor is a piece of hardware, but 95% of the work we do is in software. We have two people who put the processors on a board, but we have 15 software engineers who put the algorithm into the processor."

The company has mapped out its course, presenting last month in its booth at the RSNA show a detailed timeline for the introduction of ever-more-advanced processors. The XT 2.5 is due out in August 2001, followed by the XT 3.0 and then by the Quad XT 4.

A major change occurring in the evolving processor chips, in addition to their increasing capacity and speed, will be their diminishing size. Making the chips smaller will allow more of them to be integrated on a board.

The latest technology will be available to OEMs for integration into their own products, as well as to end users as part of TeraRecon's own workstation, the IiVS (integrated image viewing station). IiVS has received regulatory approval for sale in the U.S. and Europe. It is DICOM compatible and comes equipped with 2-D and 3-D visualization tools.

The first scanners to demonstrate a clear need for such high-powered computing are on their way.